Prospects of caching in a distributed digital library

Many independent publishers are today offering digital libraries with fulltext archives. In an attempt to provide a single user-interface to a large set of archives, DTVs Article Database Service, offers a consolidatedinterface to a geographically distributed set of archives. While this approach offers a tremendous functional advantage to a user, the delays caused by the network and queuing delays in servers make the user-perceived interactive performance poor. In this paper, we study the prospects of caching articles at the client level as wel as intermediate points as manifested by gateways that implement the interfaces to the many fulltext archives. A central research question is what the nature of the locality is in the user accesses to such a digital library. Based on access logs to drive simulations, we find that client side caching can result in a 20% hitrate. However, at the gateway level, where multiple users may access the same article, the temporal locality is poor and caching is not so relevant. We have also studied whether spatial locality can be exploited by considering to load into cache all articles in an issue, volume, or journal, if a single article is accessed, but found that spatial locality is quite poor

A GPU Register File using Static Data Compression

GPUs rely on large register files to unlock thread-level parallelism for high throughput. Unfortunately, large register files are power hungry, making it important to seek for new approaches to improve their utilization. This paper introduces a new register file organization for efficient register-packing of narrow integer and floating-point operands designed to leverage on advances in static analysis. We show that the hardware/software co-designed register file organization yields a performance improvement of up to 79%, and 18.6%, on average, at a modest output-quality degradation.Comment: Accepted to ICPP'2

14C emission from Swedish nuclear power plants and its Eeffect on the 14C levels in the environment

The radionuclide 14C is produced in all types of nuclear reactors mainly by neutron-induced reactions in oxygen (17O), nitrogen (14N) and carbon (13C). Part of the 14C created is continuously released during normal operation as airborne effluents in various chemical forms (such as CO2, CO and hydrocarbons) to the surroundings. Because of the biological importance of carbon and the long physical half-life of 14C, it is of interest to measure the releases and their incorporation into living material. The 14C activity concentrations in annual tree rings and air around two Swedish nuclear power plants (Barsebäck and Forsmark) as well as the background 14C activity levels from two reference sites in southern Sweden during 1973-1996 are presented in this report. In order to verify the reliability of the method some investigations have been conducted at two foreign nuclear sites, Sellafield fuel reprocessing plant in England, and Pickering nuclear generating station in Canada, where the releases of 14C are known to be substantial. Furthermore, results from some measurements in the vicinity of Paldiski submarine training centre in Estonia are presented. The results of the 14C measurements of air, vegetation and annual tree rings around the two Swedish nuclear power plants show very low enhancements of 14C, if at all above the uncertainty of the measurements. Even if the accuracy of the measurements of the annual tree rings is rather good (1-2%) the contribution of 14C from the reactors to the environment is so small that it is difficult to separate it from the prevailing background levels of 14C. This is the case for all sampling procedures: in air and vegetation as well as in annual tree rings. Only on a few occasions an actual increase is observed. However, although the calculations suffer from rather large uncertainties, the calculated release rate from Barsebäck is in fair agreement with reported release data. The results of this investigation show that the effective doses to man related to the releases of 14C from the Swedish light-water reactors at Barsebäck and Forsmark are very low, especially compared to the situation at other nuclear installations, such as the fuel reprocessing plant at Sellafield, England, and the heavy-water reactors at Pickering nuclear generating station, Canada. Lund/Malmö February 200

Implicit transactional memory in chip multiprocessors

Chip Multiprocessors (CMPs) are an efficient way of designing and use the huge amount of transistors on a chip. Different cores on a chip can compose a shared memory system with a very low-latency interconnect at a very low cost. Unfortunately, consistency models and synchronization styles of popular programming models for multiprocessors impose severe performance losses. Known architectural approaches to combat these losses are too complex, too specialized, or not transparent to the software. In this article, we introduce “implicit transactional memory” as a generalized architectural concept to remove such performance losses. We show how the concept of implicit transactions can be implemented at a low complexity by leveraging the multi-checkpoint mechanism of the Kilo-Instruction Processor. By relying on a general speculation substrate, it supports even the strictest consistency model – sequential consistency – potentially as effectively as weaker models and it allows multiple threads to speculatively execute critical sections, beyond barriers and event synchronizations.Postprint (published version

Solving multiprocessor drawbacks with kilo-instruction processors

Nowadays, a good multiprocessor system design has to deal with many drawbacks in order to achieve a good tradeoff between complexity and performance. For example, while solving problems like coherence and consistency is essential for correctness the way to solve processor stalls due to critical sections and synchronization points is desirable for performance. And none of these drawbacks has a straightforward solution. We show in our paper how the multi-checkpointing mechanism of the Kilo-Instruction Processors can be correctly leveraged in order to achieve a good complexity-effective multiprocessor design. Specifically, we describe a Kilo-Instruction Multiprocessor that transparently, i.e. without any software support, uses transaction-based memory updates. Our model simplifies the coherence and consistency hardware and gives the potential for easily applying different desirable speculative mechanisms to enhance performance when facing some synchronization constructs of current parallel applications.Postprint (published version

Implicit transactional memory in kilo-instruction multiprocessors

Although they have been the main server technology for many years, multiprocessors are undergoing a renaissance due to multi-core chips and the attractive scalability properties of combining a number of such multi-core chips into a system. The widespread use of multiprocessor systems will make performance losses due to consistency models and synchronization styles of popular programming models even more evident than they already are. Known architectural approaches to combat these losses are generally too complex, too specialized, or not transparent to software. In this article, we introduce implicit transactional memory as a generalized architectural concept to remove unnecessary performance losses caused by consistency models and synchronization styles. We show how the concept of implicit transactions can be implemented with low complexity by leveraging the multi-checkpoint mechanism of the Kilo-Instruction Processor. By relying on a general speculation substrate, this method supports even the strictest consistency model – sequential consistency – potentially as effectively as weaker models and it allows multiple threads to speculatively execute critical sections, beyond barriers and event synchronizations.Postprint (published version